Today’s $300 billion global semiconductor industry can attribute much of its success to an observation from Intel founder Gordon Earle Moore. Moore’s Law predicted that the number of transistors in a dense integrated circuit (microchip) doubles approximately every two years and has led to the array of technological innovation that we see around us in the form of PCs, servers, smartphones and tablets.
The underlying challenge with Moore’s Law was that there would eventually be a point where physical constraints in chip design and manufacturing would render it unviable. Indeed, it was nearly 30 years ago when the industry was enjoying seemingly abundant growth that Professor Fujio Masuoka, now CTO at Unisantis®, warned that the current two-dimensional transistor, known as ‘planar’, was set to reach such limits.
Despite three decades of innovation, we have now reached these limits and Moore’s Law is fast being challenged by the law of diminishing returns. Specifically, at the next logical step of shrinking, which is currently in the sub 14 nanometer (billionth of a meter) node category, the cost of manufacturing a microchip becomes exponentially higher. This is because it is much harder to control the performance of a two-dimensional planar transistor at this size. Consequently, semiconductor companies must invest more in R&D to overcome the problem.
The increased risk is leading to a high degree of uncertainty in the industry and, in turn, increased consolidation as certain designers, Integrated Device Manufacturers (IDMs) and fabrication plants struggle to survive.
Global semiconductors are at a stage where big macro and micro-level factors will determine future success. Unless Moore’s Law can be sustained, the impact will not only be felt within the industry but right the way across the global technology sector and the advanced economies that have been built around it.
The Logical Next Step
Based on 2D chip design, 3GHZ computers can only be made using dual cores or more. With SGT Technology®, a single core can reach above 8GHz. At this rate of performance, its application is not only widespread but holds the potential to radically transform technologies that are already set to drive exponentially high growth over the coming years. From the $50 billion connected car industry the GSMA expects we will see in 2018, to the $191 billion public services market that analyst Forrester Research has forecasted for 2020, the possibilities are boundless.
Whether it’s space exploration or care for an aging population, the past five decades of semiconductor growth have been a driving force in human progress. However, the industry has reached a crossroads in its evolution. It now needs a fresh new direction to ensure the vast potential it has already created can be sustained for generations to come. SGT Technology® offers the path to long-term growth and profitability for designers, IDMs and fabrication plants alike. For all participants in the vibrant technology sector. SGT Technology® is the logical next step.
Following 30 years of research and development, Professor Fujio Masuoka, a pioneering inventor of many breakthroughs in the semiconductor industry, including Flash Memory, has come up with a solution – the Unisantis® three dimensional Surrounding Gate Transistor.
Conventional planar transistors control the flow of electrons using a single contact gate. The more control over the channel, the better the performance, and the lower the power usage. Transistors have shrunk to the size where controlling the channel in this way is increasingly difficult.
Tri-Gate Transistors offer an improvement by moving the channel into the gate, allowing it to be controlled on three sides. The Unisantis® Surrounding Gate Transistor takes this even further, surrounding the channel on all sides, which provides the ultimate control over the channel. Surrounding Gate Transistors have a vertical design as opposed to a horizontal design – the nature of this structure enables a reduction in occupied area by 50 percent versus planar. By reducing the size and the occupied area, power consumption is decreased while access speeds are increased.
A reduction in occupied area also means reduced costs through higher yield of functioning chips per wafer. SRAM, built using SGT Technology® semiconductor products, has a lower CPU cost and lower power consumption. Ultimately, any component based on Surrounding Gate Transistor design will be faster, cheaper and more energy efficient.
The production of Surrounding Gate Transistors is possible through a low cost modification to common manufacturing processes. Foundries that are tooled for 2D planar transistors can leapfrog to three dimensional Surrounding Gate Transistors.
With such an advantage over competing designs, the Surrounding Gate Transistor holds the potential to radically transform technologies in every sector. With over 500 patents and patents pending and decades of design and process knowledge and experience, the Unisantis® Surrounding Gate Transistor is the logical next step for the semiconductor industry.
Surrounding Gate Transistor
The Surrounding Gate Transistor, has a unique three-dimensional structure in which all three electrodes of source, gate and drain are placed in the vertical plane with the gate electrode surrounding a silicon column.
SGT technology primary benefits:
- Occupies 50 percent of the area of a current chip.
- Has three times higher electron mobility.
- Provides ideal sub-threshold swing.
- Allows short-channel effect suppression.
- Offers significantly lower power consumption, higher operating speed, and much lower costs through a Surrounding Gate Transistor-based CPU.